1. Technical Field
The present disclosure relates to an integrated power circuit and the package on which such integrated circuit is placed, and particularly, but without limitation, to a switching power integrated circuit with high insensitivity to parasitic inductances of the wires for connection with a package.
2. Description of the Related Art
One known problem of power integrated circuits, that is susceptible of causing malfunctioning, is the inevitable parasitic inductance of connecting wires for connection of the integrated circuit with a package.
For example, with reference to FIG. 1, which shows a perspective view of a power integrated circuit 1 when placed on a package 2, the connection between the integrated circuit 1 and the package 2 is found to occur by means of one or more connection wires 5.
Particularly, the integrated circuit 1 may be a MOSFET power transistor or an Insulated Gate Bipolar Transistor (IGBT), whereas the package 2 may be a package having ten pins P1 -P10 for mechanical and electrical connection with the tracks of a Printed Circuit Board (not shown), and a metal back plate 3 for mechanical and electrical connection with a pad of the PCB.
Thus, connection between the integrated circuit 1 and the package 2 is ensured by a connection wire 5 that electrically connects a source pad 4 of the integrated circuit 1 with the pin P7, which is in turn connected with the PCB.
Likewise, both the drain terminal and the gate terminal of the integrated circuit 1 are connected by connection wires (not shown) to respective pins of the package 2, which are in turn electrically and mechanically connected to the metal tracks of the PCB.
As is known, if the integrated circuit is based on the MOSFET technology, the source pad 4 of the integrated circuit 1 is caused to contact the source regions of all the basic MOSFET units implemented in the integrated circuit to thereby form a single source pad 4.
Referring now to FIG. 2, which shows an electric circuit diagram of the integrated circuit 1, if the latter is constructed using the MOSFET technology, such integrated circuit has a power output stage 1A implemented by an n-channel MOS power transistor M1, which is driven through its gate terminal GM1 by a driving stage 6.
The integrated circuit 1 is arranged to be powered through a voltage generator Va, and an external load Zload is connected to the drain pad 7, i.e., the drain terminal DM1 of the transistor M1 is connected to the load Zload through the drain pad 7.
The driving circuit 6 is formed, for instance, of a voltage generator Vd and a resistor Rd connected in series.
For instance, the voltage generator Vd may be implemented as an integrated inverter system, whereas the resistor may be implemented as a MOS transistor operating in the triode region.
Still referring to FIG. 2, it shall be noted that the equivalent circuit of the parasitic inductance introduced by the connection wire 5 existing between the source pad 4 and the negative pole of the voltage generator Va is represented by the inductance Lpar.
As a complement to the description, it shall be noted that there is also a parasitic inductance in series with the load Zload but, for the purposes of the present disclosure, its effect is negligible, wherefore it is omitted for simplicity.
Assuming that the generator Vd of the drive circuit 6 generates a square-wave voltage, the current derivative ILpar flowing into the inductor Lpar in time t generates a voltage VLpar at the ends of the inductor, which is given by the following relation:VLpar=LpardILpar/dt 
In real cases, the voltage VLpar may also be of considerable value, and this may lead to malfunctions of the integrated circuit 1, not excluding any irreparable damages thereto.
Referring to FIG. 3, there is shown a waveform 8 of the voltage (in solid line) that can develop at the ends of the inductance Lpar, i.e., the voltage existing at the source pad 4, when the generator Ld drives the terminal GM1 of the transistor M1 with a voltage having, for instance, a stepped curve, ranging from 0V to 3.3V.
It can be noted that, considering the values of load, inductance Lpar, current, etc., the circuit implementation as shown in FIG. 2 can give rise to overvoltages that cause a pulsed voltage increase of the source pad 4 to values exceeding −22V.
Referring now to FIG. 4, there is shown a waveform 9 of the output voltage (in solid line) that can develop at the ends of the load impedance Zload, i.e., the voltage existing at the drain pad 7, when the generator Vd drives the terminal GM1 of the transistor M1 with a voltage having a stepped curve, with steps ranging from 0V to 3.3V.
It can be noted that the circuit implementation shown in FIG. 2 gives rise to overvoltages that cause a pulsed voltage increase at the drain pad to values of about −22V.
In prior devices, the method typically used to reduce VLpar consisted in driving the MOSFET technology output stage 1A with a voltage step having a sufficiently slow rise time so that the MOS transistor M1 and the derivative of the current to the source pad 4 can be slowed down.
The drawback of this method is that the MOS transistor M1 is typically turned on in a fixed manner, without accounting for any changes in the parasitic inductance Lpar, for the features of the load Zload, and for the MOS transistor M1 itself.
Also, the voltage that drives the MOS transistor M1 cannot be simply “shaped” to adequately control the Lpardl/dt without using costly circuit arrangements.